1. Field of the Invention
The present invention relates generally to the field of computer architecture, more specifically, to chipset support for non-uniform memory access among heterogeneous processing units.
2. Description of the Related Art
As is well-known, a central processing unit (CPU) executing an operating system (OS) can access a local system memory and/or one or more hardware devices when performing input/output (I/O) operations. The I/O operations may be routed to and from the CPU through one or more bridges, including a memory bridge (e.g., “Northbridge” chip) and/or an I/O bridge (e.g., “Southbridge” chip). The one or more hardware devices may include memory modules, computer monitors, hard disk drives, and CD-ROM drives, Universal Serial Bus (USB) controllers, PCI Express (PCIe) controllers, among others. The hardware devices may be integrated hardware devices or peripheral hardware devices.
One problem with conventional computer architectures is they are designed with the underlying assumption that there is only a single CPU included in the computer system. Accordingly, when implementing a multi-processor system using conventional architecture schemes, it is not possible for each CPU to access the physical memory associated with the other CPUs.
Another problem with conventional architectures is that the chipsets and memory controllers are typically not designed for use in a multi-processor computer system where each processor can access the local memory of the other processor.
Some prior art computer architectures attempt to overcome these drawbacks by allowing two CPUs to coexist in the computer system. However, in these prior art computer architectures, each CPU must be aware of any other CPUs in the computer system and must be specially configured to operate in the multi-processor system. Additionally, in many prior art multi-CPU systems, the multiple processors are homogeneous, meaning that they are substantially the same and/or from the same vendor.
Accordingly, there remains a need in the art for an improved technique for allowing multiple heterogeneous processing units to access the physical memory associated with other processing units in the same system.